Schottky-gate field-effect transistors are generally well known in the art and have been described, for example, by Robert G. Hunsperger et al in U.S. Pat. No. 3,912,546, assigned to the present assignee, and by James C. North et al in U.S. Pat. No. 3,700,978, assigned to the Bell Telephone Laboratories. These field-effect devices have been fabricated in both silicon and gallium arsenide and have also been referred to by the acronym, MESFET, which stands for Metal-Semiconductor Field-Effect Transistor. As a result of recent advances in the GaAs FET art which have improved the high frequency performance of these microwave devices, they have been the subject of many recent in-depth publications, such as an article by S. V. Bearse in the February, 1976 issue of MICROWAVES and entitled "Gallium Arsenide Field-Effect Transistors: Device Designers Solving Reliability Problems", at page 32 et seq. These GaAs FET devices are also described by K. Sekido et al in the April-May, 1976 issue of the M.S.N. Journal in an article entitled "Recent Advances in FET Device Performance and Reliability", at page 71 et seq. The above and other references to be identified are incorporated herein by reference.
These Schottky-gate microwave devices typically include, among other things, spaced apart source, gate and drain electrodes on the surface of an epitaxial gallium arsenide layer, with the source and drain electrodes making ohmic contact to the epitaxial gallium arsenide layer and the gate electrode making Schottky contact between the source and drain electrodes to thereby define the channel region of the device. The source and drain electrodes will typically be of a gold germanium alloy material suitable for making good ohmic contact to the GaAs, whereas aluminium is a preferred metal for use as the Schottky-gate contact for the device. The Schottky-gate electrode is adapted to receive a control or modulating gate voltage, V.sub.g, for modulating the channel conductivity and this controls the flow of current between the source and drain electrodes of the device.
In the fabrication of these gallium arsenide field-effect transistors, it has been one practice to leave the upper surface of the epitaxial gallium arsenide layer completely exposed to environmental surroundings. However, it has been observed that such an unprotected and unpassivated gallium arsenide epitaxial layer will exhibit undesirable surface states in response to applied electric fields. These surface states cause the time drift of various electrical parameters of the device under constant voltage bias conditions, and such drift is described in more detail in an article by J. S. Barrera entitled "GaAs Field Effect Transistors", Microwave Journal, Vol. 19, No. 2, February 1976. The origin of this time drift is the change of occupancy of carrier trapping centers under the influence of applied electric fields. These traps or trapping centers are located either near or at the surface of the FET device, or in the body of its conducting channel, or at the interface between the device channel and its underlying substrate. These deleterious surface and trapping effects are also described in some detail in the above-identified MSN Journal article by K. Sekido et al.
Previous attempts to reduce these undesirable device surface states have included the deposition of either (1) a layer of polycrystalline gallium arsenide (PGA) or (2) a layer of glass (such as amorphous silicon dioxide or a silicate glass) on the exposed surface of the semiconductor layer upon which the source, gate and drain electrodes are located. The deposition of polycrystalline gallium arsenide for purposes of device surface stabilization is described, for example, by D. R. Chen et al in article entitled "Long Term Stabilization of Microwave FET's", Microwave Journal, at pages 80-81. The utilization of silicon dioxide for these same surface stabilization purposes is described in the above-identified MSN Journal article by K. Sekido et al.
One disadvantage of utilizing either of the above surface-insulator approaches to device stabilization involves the difficulty in controlling and precisely reproducing these surface insulator layers in batch fabrication processes. Additionally, both of these prior art surface insulating layer deposition processes introduce certain chemical impurities into the deposited insulating layers, and this in turn creates further surface instability problems for the devices being fabricated. Furthermore, when polycrystalline gallium arsenide is deposited over the entire surface of a field-effect transistor, the desired high resistivity of the PGA layer depends upon the proper reaction of the polycrystalline gallium arsenide with the residual atmosphere in the PGA vacuum deposition system utilized. Additionally, PGA layer deposition has been known to accelerate failure of the FET electrode metallization used as a result of the increased reaction between the PGA surface insulator and the electrode metals in direct contact therewith.